A digital signal processor is a special purpose processor optimized for digital signal processing applications such as speech analysis and synthesis to produce computerized speech, image processing, or digital filtering. The digital signal processing applications tend to be intensive in memory access operations and tend to require the input and output of large quantities of data. Real-time digital signal processing requires fast hardware to perform a large number of calculations. In many algorithms, the calculations involve repetitions of a very large number of multiplication and accumulation functions. The number of these calculations, performed in real-time by the processor between individual data samples, may limit the signal processing because it limits the sampling rate. Thus, the processor is designed for high throughput numerical processing and high interrupt rates.
In general, a digital signal processor includes a core processor, at least one memory for storing instructions and operands used in operations, link port buffers for communicating with communication ports and an external port for controlling communications via an external data bus and an external address bus. The core processor includes a control block, an instruction alignment buffer connected to a primary instruction decoder, and at least one computation block for performing the digital signal processing operations. The computation unit includes a register file, a multiplier/accumulator, an arithmetic logic unit (ALU), and a shifter. The core processor may use several different computational schemes and data storage and transfer schemes for optimizing speed, accuracy, size and performance.
Usually, the shifter operates on data organized as n-bit words. The shifter receives instructions from the sequencer, receives operands from the register file, and stores operands in the register file, all operations occurring on n-bit boundaries. For example, the shifter performs a left shift in which the i-th bit is replaced by the (i+1)st bit, and performs a right shift in which the i-th bit is replaced by the (i-1)st bit. In logical shifts, the bit shifted out is lost and the bit shifted in is zero. In circular shifts, the bit shifted out of one end is shifted into the other end, thereby losing no information. In arithmetic shifts, by shifting a bit string left, the shifter multiplies by two the binary number represented by the bit string, and by shifting the bit string right, the shifter divides the binary number by two.
The register file includes a multiplicity of registers having a selected bit size for temporary storage of instructions, operands and results. The register file receives the operands from the memory and provides the operands to the multiplier, the ALU, and the shifter via several operand busses. After computation, the register file receives the results from the multiplier, the ALU, and from the shifter via several result busses. Usually, the multiplier, the ALU and the shifter operate on data that has a fixed word size. However, the fixed word size is not necessarily optimal for all digital signal processing applications.
For example, certain communication applications may use Huffman coding, which uses a variable length character encoding scheme (as opposed to character encoding schemes that use a fixed number of bits per character). The Huffman coding minimizes the total number of bits for characters appearing with the highest frequency. This coding selects the number of bits based on known probabilities so that a data string is decoded as the bits arrive in the data stream. This coding achieves a tighter packing of data since the most commonly occurring characters are short and the infrequently occurring characters are long, wherein the shortest character with the highest probability of occurrence is only one bit long. Most digital signal processors are designed to manipulate data having a fixed word size (e.g., 16-bit or 32-bit words). Such design is not optimal for implementing the Huffman coding.